Max amount of FITech students: 15 adult learners
After this course you will know how to use Verilog hardware description language (HDL) to develop digital systems.
Course contents
You will know Verilog development workflow for FPGA, including what components FPGA toolchain contains. You will know how to implement digital protocols for communication inside and outside of FPGA.
Learning outcomes
After the course the students will be able to
- develop, simulate and test Verilog designs
- implement common digital protocols for communication inside and outside of a FPGA. The protocols are implemented and tested on physical hardware.
Course materials
- Lecture material.
Teaching schedule
- Lectures and exercises online on Wednesdays at 12-16.
- Laboratory works on campus are mandatory (time agreed with students).
Completion methods
Exercises and laboratory works.
Please check the schedule from the Aalto University study guide.
You can get a digital badge after completing this course.