Back to all courses
Start here
FPGA for communication systems
Individual course
Max amount of FITech students: 15 adult learners
After this course you will know how to use Verilog hardware description language (HDL) to develop digital systems.
Course contents
You will know Verilog development workflow for FPGA, including what components FPGA toolchain contains. You will know how to implement digital protocols for communication inside and outside of FPGA.
Learning outcomes
After the course the students will be able to
- develop, simulate and test Verilog designs
- implement common digital protocols for communication inside and outside of a FPGA. The protocols are implemented and tested on physical hardware.
Course materials
- Lecture material.
Teaching schedule
- Lectures and exercises online on Wed 12-16.
- Labratory works on campus are mandatory (time agreed with students).
Completion methods
Exercises and laboratory works.
Please check the schedule from the Aalto University study guide.
You can get a digital badge after completing this course.
Responsible teacher
Aalto University
Kalle Ruttik, Senior University Lecturer
kalle.ruttik(at)aalto.fi
Contact person for applications
FITech Network University
Fanny Qvickström, Student services specialist
info(at)fitech.io
Start here
Topics:
5G technology,
Programming
Programming
Course code:
ELEC-E7555
Study credits:
5 ECTS
Price:
0 €
Course level:
Teaching period:
8.1.–28.5.2025
Application start date:
13.11.2024
Application deadline:
26.12.2024
Host university:
Aalto University
Who can apply:
Adult learner
Teaching method:
Blended
Place of contact learning:
Espoo
Teaching language:
English
General prerequisites:
Basics of communications engineering (Layer 1). Basics in programming.
Course suitable for:
Persons interested implementing new communications systems.